The present invention generally relates to an apparatus and a method for circuit design. More particularly, the present invention generally relates to an apparatus and method for automating the debug of design models and verification environments for integrated circuits.
Modern circuit design of integrated circuits (ICs) is a combination of automated design and debug of the design. ICs are often automatically designed using specialized computer program code that serves as simulation of the IC. The design of complex ICs generally requires a high level of design verification before millions of dollars are committed to the manufacture of the ICs. Design verification typically includes running a verification program on a design (often referred to as a DUV, or design under verification). Much of the verification is carried out by stimulation of the DUV at a logical level, where the DUV is modeled with one or more hardware description languages (HDLs).
A “verification environment” (VE) is created to stimulate the DUV, check the responses from the stimulated DUV, and collect coverage information used to measure the degree to which the DUV was exercised during verification. VEs are typically written in one or more verification languages, such as e, System Verilog, or SystemC.
The complexity of modern designs for complex ICs typically requires large amounts of stimulation to achieve significant test coverage of design verification (e.g., to exercise the DUV sufficiently to demonstrate that the DUV works as desired). It is not uncommon for thousands of stimulations to run for weeks on a computer farm in order to verify a specific version of a DUV. As the design process progresses, the DUV is updated and the verification task is typically repeated.
A computer farm typically contains hundreds, or even thousands of computers working together to verity a DUV. The computer farm is typically used to run verification tasks non-stop throughout the design process, which often goes on for many months.
Failures in a DUV are often encountered during stimulation of the DUV by the VE. The failures typically indicate potential problems with the DUV or the VE. The output of failure information forms an important part of the verification process as the failure information may reveal design errors of the DUV and/or the VE that need to be debugged and fixed before an IC is fabricated. Each piece of failure information output from a verification process is typically examined and diagnosed in an attempt to ensure that no errors are overlooked prior to fabrication.
The process of diagnosing failures in a DUV during the verification process is typically referred to as debug. Verification engineers typically examine raw data from a set of verification tests (often referred to as “runs”) in an attempt to locate and fix bugs in a DUV. Debugging a DUV is typically a challenging intellectual process that traditionally has been conducted by expert engineers. Continuously running stimulations generates a relatively large amount of failure data to be reviewed for DUV debug by a team of design verification experts, technicians, and the like devoted to debugging. Due to the relatively large amount of data generated by running a stimulation of a DUV these engineers and technicians spend relatively larges amount of time and mental effort to analyze data to locate bugs. The debug process is a bottleneck in the design process, which affects engineering costs and schedules for moving IC to market.
Therefore, a need exists to improve the debug process so that designers and verification engineers can reduce the time they spend debugging DUVs by developing debug methods and apparatus that automate portions of the debug process typically performed by the designers and the verification engineers.